1. Field of the Invention
The present invention relates to a semiconductor device having a bit line structure hierarchized into global bit lines and local bit lines, and relates to a control method thereof.
2. Description of Related Art
In recent years, miniaturization of memory cells has been achieved in semiconductor devices such as DRAM, and thus an increase in the number of memory cells connected to a bit line has caused a performance problem such as an increase in bit line capacitance. In order to overcome such a problem, a configuration in which the bit lines are hierarchized into global bit lines and local bit lines has been proposed. In a hierarchical memory cell array of this kind, data stored in a memory cell is read out to a local bit line and thereafter transmitted to a global bit line through a hierarchical switch. In a general DRAM, the bit lines need to be precharged to a predetermined voltage before a read operation, and therefore a configuration provided with a precharge circuit and wiring lines for a precharge voltage (precharge lines) is employed (for example, see Patent Reference 1). On the other hand, in the hierarchical memory cell array, the local bit lines and the global bit lines need to be separately precharged, and therefore a configuration in which precharge circuits and wiring lines are provided for both the local bit lines and the global bit lines should be employed. For example, a hierarchical bit line structure is known, in which a plurality of local bit lines are electrically connected to one global bit line through corresponding hierarchical switches. Normally, since there is provided a predetermined number of local bit lines corresponding to each one of the global bit lines, an area for arranging a plurality of precharge circuits and a plurality of precharge lines is required in relation to the predetermined number of local bit lines.    [Patent Reference 1] Japanese Patent Application Laid-open No. 2004-288299 (U.S. Pub. No. 2004/0204891 A1)
In general, one of the test operations for the DRAM is a voltage stress test of memory cells. The voltage stress test is performed by writing different voltages into the memory cells through adjacent bit lines to which the memory cells are connected for the purpose of determining whether or not the memory cells operate normally. Particularly, a large voltage stress can be applied to a plurality of bit lines by supplying a high voltage to odd numbered bit lines and supplying a low voltage to even numbered bit lines. However, when the voltage stress test is performed for the hierarchical memory cell array, two kinds of precharge circuits and two kinds of precharge lines need to be provided to supply at least two kinds of voltages different from each other to a plurality of local bit lines adjacent to one another that extend in the same direction. Particularly, the precharge lines extend in a direction intersecting the local bit lines, inevitably resulting in an increase in area. For example, when there are M local bit lines corresponding to each one of the global bit lines, it is only necessary to provide M precharge lines in a normal operation, and however 2M precharge lines need to be provided for the purpose of performing the voltage stress test of the memory cells. This causes a problem that the area of the memory cell array remarkably increases.